Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology\nto build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAMbased\nregisters, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of\nhard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency\nand energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different\nwrite state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling\npriority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost\nminimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost\nmodel is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed\ncost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show\nthat the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register\ndesign.
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